66 lines
1.9 KiB
Markdown
66 lines
1.9 KiB
Markdown
# ADR-0011: Memory Addressing Simplification (PA-first)
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## Status
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Accepted
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## Context
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A realistic system uses host-side virtual addressing and an MMU/IOMMU-style
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translation path for DMA: host allocates physical memory at PE level, maps it
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into a virtual address space, installs mappings, and DMA requests use virtual
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addresses that are translated to physical addresses.
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For early development, we want a minimal, deterministic model that enables:
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- correct routing and latency accounting through the graph,
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- stable tensor deployment and kernel execution semantics,
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- future extension toward VA/MMU without rewriting workflows.
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---
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## Decision
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### D1. Phase 0 model is PA-only
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The simulator uses a PA-first model:
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- All device memory accesses (MemoryRead/MemoryWrite) operate on device physical
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addresses (PA) plus size.
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- Tensor handles store PA-based shard mappings after deployment.
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- KernelLaunch passes tensor arguments as PA-based mappings (or references to them).
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- MMU/IOMMU concepts (virtual address spaces, page tables, translation latency)
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are NOT modeled in Phase 0.
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### D2. Allocation produces PA mappings
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Device allocation selects PE-local memory regions and returns PA mappings
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sufficient to execute kernels and issue DMA requests.
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### D3. Extension path (non-breaking)
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A future ADR MAY introduce an optional VA/MMU layer by:
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- introducing virtual addresses in tensor handles,
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- adding a mapping-install step,
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- modeling translation latency and page granularity.
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The Phase 0 PA model remains a valid fast-path configuration.
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---
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## Consequences
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- Early implementation stays simple and testable.
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- All latency remains explicit via graph traversal, not hidden translation.
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- Future VA/MMU modeling can be added without breaking existing benchmarks.
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---
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## Links
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- ADR-0007 (runtime_api vs sim_engine boundaries)
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- ADR-0008 (tensor deployment)
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- ADR-0009 (kernel execution)
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- SPEC R2 (latency by traversal)
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