65 lines
2.3 KiB
Markdown
65 lines
2.3 KiB
Markdown
# ADR-0004: Memory Semantics & Local-HBM Bandwidth Guarantee
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## Status
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Accepted
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## Context
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Accurately modeling PE↔HBM behavior is essential for kernel latency estimation.
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Each PE has a notion of “local HBM” that must guarantee full HBM bandwidth, independent of intervening on-die fabric bandwidth.
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## Decision
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### D1. Local HBM definition
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- Each PE is assigned a logically defined “local HBM” region.
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- Local HBM corresponds to the pseudo-channel subset directly attached to that PE’s DMA path
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via the XBAR (top or bottom, depending on PE corner placement).
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- The path is: PE_DMA → XBAR.top/bottom → HBM_CTRL.
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- The mapping (HBM pseudo-channels → PE local regions) is derived from topology configuration.
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### D2. Local HBM bandwidth guarantee contract
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- Accesses from a PE to its local HBM MUST guarantee full HBM read/write bandwidth
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independent of intervening fabric bandwidth limits.
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- This guarantee is modeled by:
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- a dedicated logical path and/or service model that enforces HBM BW at the PE-local-HBM interaction point,
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- while still incurring non-zero latency along explicitly modeled components.
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### D3. Cross-half HBM semantics
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- A PE connected to XBAR.bottom that accesses HBM pseudo-channels on the XBAR.top half
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(or vice versa) traverses a bridge:
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- PE_DMA → XBAR.bottom → bridge → XBAR.top → HBM_CTRL
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- Bridge bandwidth may limit cross-half HBM access relative to local-half access.
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### D4. Non-local HBM semantics (inter-cube / inter-SIP)
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- Accesses from a PE to HBM in a different cube or SIP MAY be limited by:
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- NOC bandwidth within the cube,
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- inter-cube UCIe links,
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- inter-SIP fabric (PCIe/UAL).
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- These paths MUST be explicit and traceable.
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### D5. Shared SRAM semantics
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- Each CUBE contains a shared SRAM accessible by all PEs in that CUBE.
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- Access path: PE_DMA → NOC → shared SRAM.
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- Shared SRAM bandwidth is limited by the NOC↔SRAM link bandwidth.
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- Shared SRAM is not part of the HBM address space; it is a separate memory domain.
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## Verification Notes
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Tests should cover:
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- local-HBM case: BW matches HBM BW regardless of fabric BW parameter
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- cross-half HBM case: latency includes bridge traversal
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- non-local cases (inter-cube/inter-SIP): BW/latency respond to fabric/link parameters
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- shared SRAM case: access via NOC with correct BW
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## Links
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- SPEC R2/R5
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- ADR-0002 (distance/order & explicit bypass)
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