ywkang
63669f82cb
- DPPolicy: 3-level (sip/cube/pe), unified naming (column_wise/row_wise) - PE_CPU: auto num_programs from cube shard count - context.launch(): per-SIP KernelLaunchMsg with local va_base + auto local shape - deploy_tensor: removed mmus param, MMU mapping is context-only responsibility - ComponentRegistry: YAML-based lazy loading (components.yaml), impls→builtin rename - VA offset bench + tests: 2D/1D, standard Triton kernel pattern Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
101 lines
3.8 KiB
Markdown
101 lines
3.8 KiB
Markdown
# ADR-0011: Memory Addressing — PA-first with VA/MMU Extension
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## Status
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Accepted (Phase 1 VA/MMU implemented)
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## Context
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A realistic system uses host-side virtual addressing and an MMU/IOMMU-style
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translation path for DMA: host allocates physical memory at PE level, maps it
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into a virtual address space, installs mappings, and DMA requests use virtual
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addresses that are translated to physical addresses.
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The PA-only model (Phase 0) was insufficient for running standard Triton kernels
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that use `base_addr + offset` patterns on sharded tensors — each PE's shard has
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a different PA, but the kernel needs a single contiguous address space.
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---
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## Decision
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### D1. Phase 0 model is PA-only (original, retained as fallback)
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- All device memory accesses (MemoryRead/MemoryWrite) operate on device physical
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addresses (PA) plus size.
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- PA-only mode remains functional via PageFault fallback in PE_DMA.
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### D2. Allocation produces PA mappings
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Device allocation selects PE-local memory regions and returns PA mappings
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sufficient to execute kernels and issue DMA requests.
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### D3. Phase 1: VA/MMU layer (implemented)
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#### D3.1 Virtual Address Model
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- Each tensor gets a single contiguous VA range (`TensorHandle.va_base`).
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- `TensorShard` does NOT carry a `va` field — shard VA is derived as
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`va_base + offset_bytes`.
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- Kernels receive `va_base` as their pointer argument (via `TensorArg.va_base`).
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- `DmaReadCmd.src_addr` and `DmaWriteCmd.dst_addr` carry VA (not PA).
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#### D3.2 PE_MMU Component
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- Hybrid design: SimPy component (inbox for MmuMapMsg) + utility (synchronous
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`translate()` called by PE_DMA).
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- Page-aligned dict lookup for O(1) VA→PA translation.
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- `tlb_overhead_ns` configurable per-access latency.
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- PageFault fallback: if VA has no mapping, PE_DMA treats it as PA directly
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(backward compatibility with PA-only tests).
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#### D3.3 Mapping Installation
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- `MmuMapMsg` traverses the fabric: Host → PCIE_EP → IO_CPU (cube fan-out) →
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M_CPU (PE fan-out) → NOC → PE_MMU. Latency is measured end-to-end.
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- `MmuMapMsg.target_sips` controls SIP-level routing to prevent cross-SIP
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mapping contamination for replicated tensors.
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- Mapping strategy based on `DPPolicy.cube`:
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- **Replicate** (`cube="replicate"`): per-(sip, cube) local mapping only.
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Each cube's PEs see only their local PA. No cross-cube mapping installed.
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- **Sharded** (`cube="column_wise"`, etc.): broadcast all shard mappings to all
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target cubes. Enables cross-PE and cross-cube DMA.
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#### D3.4 Tensor Lifecycle
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- `del tensor` triggers automatic cleanup via `Tensor.__del__` + `weakref` to
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RuntimeContext. Sends `MmuUnmapMsg` through fabric, returns VA and PA space.
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- `with RuntimeContext(...) as ctx:` provides scope-based bulk cleanup.
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- `RuntimeContext._tensors` uses `weakref.ref` to avoid preventing GC.
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- `PEMemAllocator` uses free-list with coalescing (not bump allocator).
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- `VirtualAllocator` uses free-list with coalescing for VA space.
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#### D3.5 Allocators
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- `VirtualAllocator`: device-wide VA space, page-aligned alloc/free with
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coalescing.
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- `PEMemAllocator`: per-PE HBM/TCM, free-list based alloc/free with coalescing.
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- Page size configurable via `topology.yaml` pe_mmu attrs (default 4096).
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---
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## Consequences
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- Triton kernels use `base_addr + offset` patterns naturally on sharded tensors.
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- All latency remains explicit via graph traversal, including MMU mapping
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installation and per-access TLB overhead.
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- PA-only mode retained as fallback (PageFault → treat as PA).
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- Benchmark parameter renamed `ctx` → `torch` for PyTorch code compatibility.
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- IPCQ and other fixed-address resources bypass MMU (use PA directly).
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---
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## Links
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- ADR-0007 (runtime_api vs sim_engine boundaries)
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- ADR-0008 (tensor deployment)
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- ADR-0009 (kernel execution)
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- ADR-0014 (PE-internal execution model)
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- ADR-0015 (component port/wire model)
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- SPEC R2 (latency by traversal)
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