ywkang
998cc85762
Major changes:
PE-level IPCQ infrastructure:
- New PE_IPCQ component: ring-buffer control plane with 4-direction
neighbor mapping, head/tail pointers, backpressure (poll/sleep).
- PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA,
including in-flight data snapshot (D9) and op_log recording at
outbound time for Phase 2 replay correctness.
- IpcqDmaToken piggyback model: data + metadata travel together,
atomic visibility at receiver (invariant I6).
- Credit return fast path: bottleneck-BW latency, no fabric vc_comm.
Phase 2 data execution (ADR-0020 integration):
- op_log extended: DmaWriteCmd now captures src_space/src_addr for
Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time.
- DataExecutor replays dma_write + ipcq_copy in t_start order.
- Engine._flush_data_phase: incremental cursor-based replay after
each engine.wait() so host reads see post-Phase-2 data.
- KernelRunner Phase 1 writes disabled when op_log is active to
prevent stale data from corrupting the MemoryStore snapshot.
TLContext / kernel API:
- tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype),
tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode.
- TensorHandle operator overloading (add/sub/mul/div) via thread-local
active TLContext → MathCmd dispatch through PE_MATH.
- PE-local scratch allocator for math output handles.
- tl.load returns space="hbm" handles for correct Phase 2 addressing.
- Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv.
Unified ccl_allreduce bench (PyTorch-compat host code):
- Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch)
split matching real PyTorch DDP worker pattern.
- torch.distributed facade: init_process_group, get_world_size,
get_rank, get_backend, all_reduce, barrier — only real PyTorch names.
- AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches
kernel via tensor shard metadata (n_elem from shards[0].nbytes).
- world_size derived from topology spec (sips × cubes × pes_per_cube)
with optional algorithm-level override in ccl.yaml.
Tensor API (PyTorch-compat surface):
- Tensor.numpy(): gather-aware (all shards via VA-based addressing).
- Tensor.copy_(source): scatter from host tensor into sharded target.
- RuntimeContext.from_numpy(arr): host-side staging tensor.
- Tensor.data property fixed to use numpy() (was shards[0]-only).
Algorithm modules moved to src/kernbench/ccl/algorithms/:
- ring_allreduce, mesh_allreduce, tree_allreduce, hello_send.
- Each module exports kernel_args(world_size, n_elem) helper.
- ccl.yaml module paths updated to kernbench.ccl.algorithms.*.
Dead code removed:
- 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.).
- _run_ccl_bench greenlet-per-SIP scheduler.
- benches.loader.is_ccl_bench + run_rank detection.
- benches/ccl/ directory.
Tests:
- New test_ccl_allreduce_matrix.py: 7 parametrized cases
(ring×3 buffers, ring 8/16, mesh 4, tree 7).
- New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests.
- Existing tests updated for new import paths + world_size_override.
Docs:
- Korean ccl-author-guide.md and ADR-0023 paths updated.
- New English versions: ccl-author-guide.en.md, ADR-0023.en.md.
502 tests pass.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
62 lines
2.0 KiB
Python
62 lines
2.0 KiB
Python
from pathlib import Path
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from kernbench.topology.builder import _read_spec, resolve_topology
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TOPOLOGY_PATH = Path(__file__).parent.parent / "topology.yaml"
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def test_topology_yaml_loads_without_error():
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# _compile_graph is still stubbed (returns None); load must not raise
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resolve_topology(str(TOPOLOGY_PATH))
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def test_pe_layout_structure():
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spec = _read_spec(TOPOLOGY_PATH)
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pe_layout = spec["cube"]["pe_layout"]
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assert set(pe_layout["corners"]) == {"NW", "NE", "SW", "SE"}
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assert pe_layout["pe_per_corner"] == 2
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# derived total must equal original pe_per_cube: 8
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assert pe_layout["pe_per_corner"] * len(pe_layout["corners"]) == 8
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def test_pe_template_components():
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spec = _read_spec(TOPOLOGY_PATH)
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comps = spec["cube"]["pe_template"]["components"]
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assert set(comps.keys()) == {
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"pe_cpu", "pe_scheduler", "pe_dma", "pe_fetch_store",
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"pe_gemm", "pe_math", "pe_mmu", "pe_tcm", "pe_ipcq",
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}
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def test_pe_template_links_present():
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spec = _read_spec(TOPOLOGY_PATH)
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links = spec["cube"]["pe_template"]["links"]
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required = {
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"pe_cpu_to_scheduler_mm",
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"scheduler_to_dma_mm",
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"scheduler_to_gemm_mm",
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"scheduler_to_math_mm",
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"dma_to_tcm_bw_gbs", "dma_to_tcm_mm",
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"gemm_to_tcm_bw_gbs", "gemm_to_tcm_mm",
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"math_to_tcm_bw_gbs", "math_to_tcm_mm",
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}
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assert required.issubset(set(links.keys()))
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def test_pe_dma_not_in_cube_components():
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spec = _read_spec(TOPOLOGY_PATH)
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assert "pe_dma" not in spec["cube"]["components"]
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def test_pe_per_cube_removed():
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spec = _read_spec(TOPOLOGY_PATH)
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assert "pe_per_cube" not in spec["cube"].get("device", {})
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def test_shared_resource_accel_slot():
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# ADR-0014 D4: PE_GEMM and PE_MATH share PE_ACCEL capacity = 1
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spec = _read_spec(TOPOLOGY_PATH)
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comps = spec["cube"]["pe_template"]["components"]
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assert comps["pe_gemm"]["attrs"]["shared_resource"] == "accel_slot"
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assert comps["pe_math"]["attrs"]["shared_resource"] == "accel_slot"
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