d75da439c6
- Probe CLI: restructured output (tables first, routes below), per-hop timestamps, split cross-cube into best/worst cases, D2H read section - UCIe overhead: 1ns -> 8ns per port (16ns per crossing) to fix cross-cube-best < cross-half latency inversion - HBM efficiency: added efficiency=0.8 factor to hbm_ctrl, reducing effective BW from 256 to 204.8 GB/s - Multi-size BW sweep: saturation tables (4KB-1MB) for all probe cases - Probe default data size: 4KB -> 32KB for more realistic measurements - IOChiplet NOC + D2H topology and tests - NOC mesh, xbar, BW occupancy components and tests - Cube mesh visualization diagram 278 tests pass. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
180 lines
5.8 KiB
Python
180 lines
5.8 KiB
Python
"""Tests for the SimPy component model and DI registry (ADR-0007 D3).
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Phase 1 verification: all tests FAIL until Phase 2 implements production code.
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Latency invariant after refactor:
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total_ns = Σ(wire propagation) + Σ(component.run() overhead_ns) + nbytes / bottleneck_bw
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This is identical to the current formula for Phase 0 (no contention).
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"""
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import pytest
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import simpy
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from pathlib import Path
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from kernbench.components.base import ComponentBase, ComponentRegistry
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from kernbench.components.impls.forwarding import TransitComponent
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from kernbench.policy.address.phyaddr import PhysAddr
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from kernbench.runtime_api.kernel import MemoryReadMsg
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from kernbench.sim_engine.engine import GraphEngine
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from kernbench.topology.builder import load_topology
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from kernbench.topology.types import Node
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TOPOLOGY_PATH = Path(__file__).parent.parent / "topology.yaml"
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def _graph():
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return load_topology(TOPOLOGY_PATH)
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def _hbm_pa(pe_id: int = 0) -> int:
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slice_bytes = 48 * (1 << 30) // 8
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pa = PhysAddr.pe_hbm_addr(
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rack_id=0, sip_id=0, cube_id=0, pe_id=pe_id,
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pe_local_hbm_offset=0x1000, slice_size_bytes=slice_bytes,
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)
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return pa.encode()
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def _node(impl: str, overhead_ns: float = 0.0) -> Node:
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return Node(id="test", kind="xbar", impl=impl, attrs={"overhead_ns": overhead_ns}, pos_mm=None)
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# ── 1. unknown impl → error ──────────────────────────────────────────
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def test_registry_unknown_impl_raises_error():
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"""Unregistered impl raises ValueError (no fallback)."""
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node = _node("totally_unknown_v99", overhead_ns=5.0)
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with pytest.raises(ValueError, match="No component registered"):
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ComponentRegistry.create(node)
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# ── 2. TransitComponent yields exactly overhead_ns via simpy timeout ──
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def test_transit_component_yields_overhead_ns():
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"""TransitComponent.run() yields exactly node.attrs['overhead_ns'] ns."""
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node = _node("xbar_v1", overhead_ns=3.0)
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comp = TransitComponent(node)
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env = simpy.Environment()
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def proc():
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yield from comp.run(env, nbytes=4096)
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env.process(proc())
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env.run()
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assert env.now == pytest.approx(3.0)
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def test_transit_component_zero_overhead_ns():
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"""TransitComponent with overhead_ns=0 still yields (no infinite loop)."""
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node = _node("noc_v1", overhead_ns=0.0)
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comp = TransitComponent(node)
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env = simpy.Environment()
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done = []
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def proc():
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yield from comp.run(env, nbytes=1024)
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done.append(True)
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env.process(proc())
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env.run()
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assert done == [True]
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assert env.now == pytest.approx(0.0)
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# ── 3. DI override: custom component is invoked by engine ────────────
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def test_engine_component_override_is_called():
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"""Custom component injected via component_overrides is invoked during simulation."""
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class SpyXbar(ComponentBase):
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calls = 0
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def run(self, env, nbytes):
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SpyXbar.calls += 1
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yield env.timeout(0)
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SpyXbar.calls = 0
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graph = _graph()
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engine = GraphEngine(graph, component_overrides={"xbar_v1": SpyXbar})
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msg = MemoryReadMsg(
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correlation_id="c", request_id="r",
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src_sip=0, src_cube=0, src_pe=0,
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src_pa=_hbm_pa(pe_id=0), nbytes=4096,
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)
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h = engine.submit(msg)
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engine.wait(h)
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# Path passes through xbar_top (impl=xbar_v1)
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assert SpyXbar.calls > 0
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# ── 4. behavior unchanged: total_ns matches existing formula ─────────
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def test_engine_component_model_latency():
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"""MemoryRead D2H latency for local cube0 (4096B).
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Bypass path (m_cpu bypass): pcie_ep → io_noc → conn → io_ucie → cube_ucie
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→ conn → noc → xbar_top → hbm_ctrl.slice0
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Path goes through xbar_top (overhead_ns=2.0) instead of per-PE xbar.
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Latency must be positive and reasonable.
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"""
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graph = _graph()
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engine = GraphEngine(graph)
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msg = MemoryReadMsg(
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correlation_id="c", request_id="r",
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src_sip=0, src_cube=0, src_pe=0,
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src_pa=_hbm_pa(pe_id=0), nbytes=4096,
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)
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h = engine.submit(msg)
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engine.wait(h)
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_, trace = engine.get_completion(h)
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# Verify positive latency; exact value depends on path through xbar_top
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assert trace["total_ns"] > 0
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# ── 5. override is scoped: only targeted impl is replaced ────────────
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def test_engine_override_is_scoped_to_impl():
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"""xbar_v1 override (ZeroXbar, no overhead_ns) reduces total_ns.
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xbar_top has overhead_ns=2.0 base + position-dependent distance.
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It is traversed on both the forward path and the reverse response path,
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so replacing it with a zero-latency impl removes all XBAR latency.
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With position-aware XBAR, the diff is >= 4.0ns (base) + distance contribution.
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"""
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class ZeroXbar(ComponentBase):
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def run(self, env, nbytes):
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yield env.timeout(0)
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graph = _graph()
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engine_default = GraphEngine(graph)
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engine_override = GraphEngine(graph, component_overrides={"xbar_v1": ZeroXbar})
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msg = MemoryReadMsg(
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correlation_id="c", request_id="r",
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src_sip=0, src_cube=0, src_pe=0,
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src_pa=_hbm_pa(pe_id=0), nbytes=4096,
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)
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h_d = engine_default.submit(msg)
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engine_default.wait(h_d)
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_, t_default = engine_default.get_completion(h_d)
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h_o = engine_override.submit(msg)
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engine_override.wait(h_o)
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_, t_override = engine_override.get_completion(h_o)
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# ZeroXbar removes base overhead_ns=2.0 + distance-based latency per traversal.
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# Forward + response = 2 traversals, so diff >= 4.0ns (base only).
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diff = t_default["total_ns"] - t_override["total_ns"]
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assert t_override["total_ns"] < t_default["total_ns"]
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assert diff >= 4.0 - 0.01, f"Expected diff >= 4.0ns, got {diff:.4f}ns"
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