ywkang
fc6abbc8ee
- CHANGES.md: detailed changelog for release 1 and 2 - README.md: full project docs with install, probe, run, test usage - SPEC.md: add ADR-0014~0017 references, update R7 for pcie_ep endpoint - ADR-0003: update NOC description to reference ADR-0017 - ADR-0004: add HBM efficiency factor (0.8) to BW guarantee contract - ADR-0014: status Proposed -> Accepted - ADR-0015: update D4 to M_CPU bypass for Memory R/W, add ADR-0016/0017 links - ADR-0016 (new): IOChiplet NOC and memory data path - ADR-0017 (new): Cube NOC 2D mesh architecture - Fix MD lint warnings (unfenced code blocks) across all docs Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
68 lines
2.3 KiB
Markdown
68 lines
2.3 KiB
Markdown
# ADR-0003: Target System Hierarchy & Modeling Scope
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## Status
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Accepted
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## Context
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We need a system-level simulator to evaluate LLM kernel performance on our AI Accelerator platform.
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The platform is organized as a compute tray containing multiple identical SIPs connected via PCIe or UAL
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through switching fabrics, with a host CPU issuing commands/kernels.
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## Decision
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We model the system hierarchy explicitly:
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### D1. Tray-level
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- A compute tray contains:
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- Host CPU (issues requests / coordinates runtime & data placement)
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- Multiple identical SIPs (accelerators)
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- Interconnect fabric between SIPs (PCIe and/or UAL via switches)
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### D2. SIP-level
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- A SIP is a multi-die package composed of:
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- Multiple CUBEs (HBM die + compute PEs + UCIe)
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- One or more IO chiplets (host/SIP interfaces)
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- IO chiplets:
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- provide interfaces: PCIe-EP, IO_CPU, optionally UAL-EP
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- can be multiple per SIP
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- placement constrained to SIP shoreline (top/bottom/left/right); each shoreline may host 1–2 IO chiplets
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### D3. CUBE-level
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- A CUBE contains:
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- HBM + memory controller (HBM_CTRL)
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- XBAR (top/bottom): HBM pseudo-channel crossbar, PE's dedicated path to HBM
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- Bridge (left/right): connects XBAR.top ↔ XBAR.bottom for cross-half HBM access
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- NOC: 2D mesh router grid spanning the entire cube with XY routing and
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per-segment contention modeling; carries all intra-cube traffic including
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PE DMA to xbar (HBM), inter-cube (UCIe), command (M_CPU↔PE_CPU), and
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shared SRAM access. See ADR-0017 for full NOC architecture.
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- Shared SRAM: cube-level shared memory accessible by all PEs via NOC
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- management/control CPU (M_CPU) coordinating PE command distribution and completion aggregation
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- multiple PEs
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- up to 4 UCIe endpoints (N/E/W/S) for CUBE↔CUBE and CUBE↔IO connectivity
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### D4. PE-level
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- A PE can execute one kernel instance
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- PE contains internal control + accelerators (modeled at PE view granularity):
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- PE_CPU, command handler, PE_TCM, DMA/GEMM/MATH engines, internal queues
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## Consequences
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- The simulator supports abstraction by “views”:
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- SIP view hides PE internals
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- CUBE view treats each PE as a single block
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- PE view expands PE internals
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- Topology remains parameterized; sizes/counts/links come from configuration.
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## Links
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- SPEC R3/R5
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- ADR-0005 (diagram views)
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- ADR-0017 (cube NOC 2D mesh architecture)
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