ywkang
687c98086d
Filename + lifecycle:
- ADR rename to ADR-NNNN-<cat>-title.md with 8 3-letter category prefixes
(dev / mem / lat / prog / algo / par / api / ver). Numbers stay immutable.
- ADR Lifecycle split into 3 folders, documented in CLAUDE.md Part 2:
docs/adr/ (Accepted), docs/adr-proposed/ (Proposed/Stub/Draft),
docs/adr-history/ (Superseded/Merged). Status field gains "Draft" for
retroactive docs pending verification.
Merges (one ADR per topic, no change-history annotations):
- ADR-0017 absorbs ADR-0019 (Cube NOC + per-PE HBM connectivity, 10 D-items)
- ADR-0014 absorbs ADR-0021 (PE pipeline execution model, 8 D-items incl.
TileToken self-routing and multi-op composite epilogue scope)
- ADR-0023 absorbs docs/ipcq-dma-codesign-hw.md as new "HW Realization
Notes (Informative)" section (D16-D23 + Open HW Questions). codesign-hw.md
deleted; ADR-0019/0021 moved to adr-history with one-line stub status
Retroactive documentation (G4 closures, code-verified):
- ADR-0037 forwarding component (TransitComponent: first-flit overhead,
serial worker, path-based routing, single impl/multiple names)
- ADR-0036 IO_CPU component (target_start_ns global barrier stamping,
per-cube fan-out, response aggregation)
- ADR-0035 M_CPU & M_CPU.DMA component (3 fan-out paths, DMA Resources,
target_start_ns passthrough)
- ADR-0034 HBM controller internal design (per-PC state, address-based
selection, flit-aware per-flit commit, async finalize, command-only
fallback path)
Content updates:
- ADR-0010 expanded to full CLI surface (run/probe/web), retitled
"Command Line Interface and Execution Semantics"
- ADR-0007 D2 rewritten to current state; ADR-0015 supersession notes pruned
- ADR-0005 wrapped in Decision header with D1-D5; ADR-0022 metadata
block replaced with standard Status header
- ADR-0024 trimmed to rank=SIP launcher essentials (D1-D4);
ADR-0027 cleaned of supersession history
- ADR-0033 D6 cleanup: address-based PC selection moved out of future-work
(now documented in ADR-0034 D3); related D1/D3 wording realigned
- Cross-references back-filled in 5 ADRs (G3 gaps closed)
Onboarding docs split:
- docs/onboarding/ created
- moved: hw-architecture-overview.md, latency-model.md, di-presentation.md,
ccl-author-guide{,.en}.md
- references updated in README, ADR-0023{,.en}, src/kernbench/ccl/__init__.py
Source / test / yaml: ADR-NNNN cross-references in docstrings and YAML
comments updated after the merges (ADR-0021->0014 D6, ADR-0019->0017 D8).
No behavior change.
Tooling:
- tools/verify_adr_lang_pairs.py + tests/test_verify_adr_lang_pairs.py
(ADR EN/KO pair invariant checker)
- .claude/commands/report.md tracked (/report slash command)
- .gitignore: allow .claude/commands/*.md while keeping settings files ignored
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
96 lines
2.7 KiB
Markdown
96 lines
2.7 KiB
Markdown
# ADR-0007: Runtime API and Simulation Engine Boundaries
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## Status
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Accepted
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## Context
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The simulator consists of multiple layers with distinct responsibilities:
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- a host-facing API layer used by benchmarks and user code,
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- a discrete-event simulation engine that executes requests,
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- device components that model hardware behavior.
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Without strict boundaries, orchestration logic can leak into components,
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or simulation internals can become entangled with user-facing APIs.
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This ADR defines clear responsibility boundaries between:
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- runtime API,
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- simulation engine (sim_engine),
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- hardware components.
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---
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## Decision
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### D1. Runtime API is host-facing orchestration only
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The runtime API represents host/driver-level behavior and MUST:
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- expose high-level operations (tensor deployment, kernel launch),
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- submit requests only to endpoint components (e.g., IO_CPU),
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- await completion via futures/handles,
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- own and persist host-side metadata (tensor allocation maps, kernel bindings).
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The runtime API MUST NOT:
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- hardcode hop-by-hop routing or fan-out,
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- directly invoke internal components (M_CPU, PE_CPU, engines),
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- embed topology- or routing-specific assumptions.
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---
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### D2. Simulation engine wires components and tracks completion
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The simulation engine (sim_engine) MUST:
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- wire components at initialization (create port stores + start wire
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processes per the component port/wire framework — ADR-0015),
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- inject requests into the compiled topology graph at entry components
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(e.g., PCIE_EP for memory operations, IO_CPU for kernel launch),
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- schedule and execute events using a discrete-event model,
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- manage correlation ids and completion tracking.
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The simulation engine MUST NOT:
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- define tensor semantics,
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- define kernel execution policies,
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- expose internal graph details to the runtime API,
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- walk the topology path during request execution,
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- call component `run()` methods directly,
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- track per-hop latency or decompose fan-out (components own this).
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---
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### D3. Components own fan-out and aggregation
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Device-side components MUST:
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- fan-out requests to downstream domains
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(IO_CPU → M_CPU → PE_CPU → schedulers/engines),
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- aggregate completion and failure signals,
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- propagate results deterministically upstream.
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Neither the runtime API nor the simulation engine may orchestrate
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component-level fan-out explicitly.
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---
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## Consequences
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- Runtime APIs remain stable as topology and routing evolve.
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- Simulation internals can change without affecting user-facing code.
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- Component implementations remain swappable via DI.
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---
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## Links
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- SPEC R4, R7, R8
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- ADR-0008 (Tensor deployment)
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- ADR-0009 (Kernel execution)
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- ADR-0015 (Component port/wire model and engine role)
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- ADR-0010 (CLI surface and execution semantics — runtime API consumer)
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