ywkang
687c98086d
Filename + lifecycle:
- ADR rename to ADR-NNNN-<cat>-title.md with 8 3-letter category prefixes
(dev / mem / lat / prog / algo / par / api / ver). Numbers stay immutable.
- ADR Lifecycle split into 3 folders, documented in CLAUDE.md Part 2:
docs/adr/ (Accepted), docs/adr-proposed/ (Proposed/Stub/Draft),
docs/adr-history/ (Superseded/Merged). Status field gains "Draft" for
retroactive docs pending verification.
Merges (one ADR per topic, no change-history annotations):
- ADR-0017 absorbs ADR-0019 (Cube NOC + per-PE HBM connectivity, 10 D-items)
- ADR-0014 absorbs ADR-0021 (PE pipeline execution model, 8 D-items incl.
TileToken self-routing and multi-op composite epilogue scope)
- ADR-0023 absorbs docs/ipcq-dma-codesign-hw.md as new "HW Realization
Notes (Informative)" section (D16-D23 + Open HW Questions). codesign-hw.md
deleted; ADR-0019/0021 moved to adr-history with one-line stub status
Retroactive documentation (G4 closures, code-verified):
- ADR-0037 forwarding component (TransitComponent: first-flit overhead,
serial worker, path-based routing, single impl/multiple names)
- ADR-0036 IO_CPU component (target_start_ns global barrier stamping,
per-cube fan-out, response aggregation)
- ADR-0035 M_CPU & M_CPU.DMA component (3 fan-out paths, DMA Resources,
target_start_ns passthrough)
- ADR-0034 HBM controller internal design (per-PC state, address-based
selection, flit-aware per-flit commit, async finalize, command-only
fallback path)
Content updates:
- ADR-0010 expanded to full CLI surface (run/probe/web), retitled
"Command Line Interface and Execution Semantics"
- ADR-0007 D2 rewritten to current state; ADR-0015 supersession notes pruned
- ADR-0005 wrapped in Decision header with D1-D5; ADR-0022 metadata
block replaced with standard Status header
- ADR-0024 trimmed to rank=SIP launcher essentials (D1-D4);
ADR-0027 cleaned of supersession history
- ADR-0033 D6 cleanup: address-based PC selection moved out of future-work
(now documented in ADR-0034 D3); related D1/D3 wording realigned
- Cross-references back-filled in 5 ADRs (G3 gaps closed)
Onboarding docs split:
- docs/onboarding/ created
- moved: hw-architecture-overview.md, latency-model.md, di-presentation.md,
ccl-author-guide{,.en}.md
- references updated in README, ADR-0023{,.en}, src/kernbench/ccl/__init__.py
Source / test / yaml: ADR-NNNN cross-references in docstrings and YAML
comments updated after the merges (ADR-0021->0014 D6, ADR-0019->0017 D8).
No behavior change.
Tooling:
- tools/verify_adr_lang_pairs.py + tests/test_verify_adr_lang_pairs.py
(ADR EN/KO pair invariant checker)
- .claude/commands/report.md tracked (/report slash command)
- .gitignore: allow .claude/commands/*.md while keeping settings files ignored
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
101 lines
2.7 KiB
Markdown
101 lines
2.7 KiB
Markdown
# ADR-0008: Tensor Deployment and Allocation (Host Allocator, PA-first)
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## Status
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Accepted
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## Context
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Benchmarks require PyTorch-like tensor semantics:
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- tensor creation (empty, fill),
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- deployment to accelerator devices (tensor.to()).
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In the realistic system, host software manages allocation/mapping and installs
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mappings for DMA/MMU. For Phase 0 we simplify (ADR-0011):
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- device memory operations use PA only,
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- VA/MMU/IOMMU is not modeled.
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To keep the host↔device interface minimal, we avoid a separate
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AllocateTensorMeta message. Instead, host allocation produces a PA shard map
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that is used directly by MemoryWrite/Read and KernelLaunch.
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---
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## Decision
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### D1. Tensor is a host-owned handle with PA shard mapping
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A Tensor object is a host-owned handle that encapsulates:
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- shape and dtype,
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- initialization intent,
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- device placement and allocation metadata as a PA shard map.
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After deployment, the Tensor handle MUST contain:
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- a list of shards, each with (sip,cube,pe,pa,nbytes,offset_bytes).
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This PA shard mapping is the single source of truth for kernel argument binding.
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---
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### D2. Deployment uses a host allocator (Phase 0)
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In Phase 0, tensor deployment produces PA shard mappings via a host allocator:
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- placement (split/replicate/hybrid) is decided by a DP policy,
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- allocation assigns PA ranges at the PE level and returns shard mappings,
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- the Tensor handle stores the resulting shard list deterministically.
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No separate host-visible device allocation RPC is required in Phase 0.
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---
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### D3. Data initialization and transfer uses MemoryWrite/Read only
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Any data initialization or transfer implied by a tensor (e.g., fill, copy)
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MUST be represented using Host ↔ IO_CPU messages only:
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- MemoryWrite
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- MemoryRead
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Rules:
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- MemoryWrite/Read MUST reference PA + (sip,cube,pe) tags (ADR-0012).
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- Allocation metadata MUST NOT be embedded as a separate allocation message.
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- Bulk tensor data MUST NOT be embedded in Phase 0 messages.
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The simulation engine schedules MemoryWrite/Read through the graph so that
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latency is computed by explicit traversal.
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---
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### D4. Extension path (non-breaking)
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Future ADRs MAY introduce optional VA/MMU/IOMMU modeling by adding:
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- virtual addressing in tensor handles,
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- mapping install steps,
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- translation latency/page granularity.
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The Phase 0 PA shard map remains a valid fast-path configuration.
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---
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## Consequences
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- Host↔IO_CPU contract remains minimal (MemoryRead/Write + KernelLaunch).
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- KernelLaunch can pass per-PE data placement explicitly via shard tags.
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- Early implementation stays simple and testable.
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---
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## Links
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- ADR-0011 (Memory Addressing — PA / VA / LA)
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- ADR-0012 (Host↔IO_CPU schema)
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- ADR-0007 (runtime_api vs sim_engine boundaries)
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- ADR-0009 (Kernel execution)
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